Power metal oxide semiconductor field effect transistors (MOSFETs) are commonly used power devices due to their low gate drive power, fast switching speed and superior paralleling capability. A trench gate of a MOSFET device typically includes a trench extending into a semiconductor substrate from the source to the drain and having sidewalls and a floor that are each lined with a layer of an insulator such as thermally grown silicon dioxide. The lined trench is filled with doped polysilicon that acts as the gate. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in a MOSFET channel extending along the sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the channel's contribution to on-resistance.
A high density trench MOSFET device also includes a contact trench in a mesa region between adjacent gate trenches to provide contact to source and body regions. Conventional processes for manufacturing trench MOSFET devices have used separate mask processes to define the gate and contact trenches. However, a mask overlay issue occurs when forming a vertical MOSFET structure because a well-controlled spacing between the gate trench and nearby contact trench is required for high density MOSFET devices, which have increasingly smaller dimensions. Schemes based on self-alignment processes have been proposed to solve this mask overlay issue. However, these proposed schemes use spacers formed below the surface of the semiconductor substrate to create a self-aligned contact trench. As a result, a lot of original silicon is lost in the mesa regions between the contract trenches. In addition, the proposed schemes use many process steps and are complicated to implement.
It is within this context that embodiments of the present invention arise.